Adaptive locks: Combining transactions and locks for efficient concurrency

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 3-14

  Usui, Takayuki ^a   Behrends, Reimer ^a   Evans, Jacob ^b   Smaragdakis, Yannis ^b  

^a UNIVERSITY OF OREGON   (United States)

^b University of Massachusetts Amherst   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVITY; C COMPILERS; COARSE-GRAINED; CONCURRENT PROGRAMMING; CRITICAL SECTIONS; I/O OPERATIONS; LOCK-BASED SYNCHRONIZATION; LOCKING TECHNIQUE; MEMORY ACCESS; MUTEXES; PROGRAMMING MODELS; TRANSACTIONAL MEMORY; TWO-COMPONENT;

COMPUTER PROGRAMMING; COST BENEFIT ANALYSIS; PARALLEL ARCHITECTURES; STORAGE ALLOCATION (COMPUTER);

LOCKS (FASTENERS);

EID: 70449645330     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.20     Document Type: Conference Paper

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