Effectiveness of internal vs. external sed scrubbing mitigation strategies in a xilinx FPGA: Design, test, and analysis

Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Volumn , Issue , 2007, Pages

  Berg, Melanie ^a   Poivey, C ^a   Petrick, D ^a   Espinosa, D ^a   Lesea, Austin ^b   LaBel, K ^a   Friendlich, M ^a   Kim, H ^a   Phan, Anthony ^a  

^a NASA GODDARD SPACE FLIGHT CENTER   (United States)

^b XILINX INC   (United States)

Author keywords

FPGA; Reconfiguration; Scrubbing; Xilinx

Indexed keywords

HEAVY-ION DATA; MITIGATION SCHEMES; MITIGATION STRATEGY; XILINX FPGA;

RADIATION EFFECTS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70449642980     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RADECS.2007.5205603     Document Type: Conference Paper

References (16)

1. Actel Datashcct: "RTAX-S/SL RadTolerant FPGAs" http://www.actel.com/documents/RTAXS-DS.pdf, V5.2, October 2007.
2. "Xilinx Virtex-5 Data sheet: DC and Switching Characteristics" http://www.xilinx.com/support/documentation/data-sheets/ds202.pdf
3. "Xilinx Virtex-4 Data sheet: and Switching Characteristics" http://www.xilinx.com/support/documentation/data-sheets/ds302.pdf
4. Les Jones XAPP714 (V1.5) : "Single Event Upset (SEU) Detection and Correction using Virtex 4 Devices.". Jan. 2007. http://www.xilinx.com/ bvdocs/appnotes/xapp714.pdf
5. A. Lesea and K. Castellani-Coulie, "Experimental Approach of Soft Error Effects in 90 nm Xilinx FPGA and Beyond," presented at RADECS 2007, Deauville, Sept. 2007.
6. M. Berg, "The NASA Goddard Space Flight Center Radiation Effects and Analysis Group Virtex-4 Scrubber", presented at Xilinx Insertion Meeting, Albuquerque, NM, June 2007. http://nepp.nasa.gov/workshops/xilinx/June2007S tatus/Pres-ll .ppt#1.
7. F. Kastensmidt, "SEE Mitigation Strategies for Digital Circuit Design Applicable to ASIC and FPGAs", Part II of the Short Course presented at the 2007 Nuclear and Space Radiation Effects Conference, Honolulu, HI, July, 23, 2007.
8. M. Berg, "Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event upset Susceptibility" , IEEE International On-Line Test Symposium, 2006.pp 89-91.
9. Xilinx Virtex Series User guide : "Virtex-4 Configuration Guide" http://www.xilinx.com/support/documentation/user-guides/ug071.pdf
10. M. Berg et.al. "An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAXS Family Field Programmable Gate Arrays," IEEE Trans. Nucl. Sci., vol. 53, n° 6, Dec. 2006.
11. J.Benedetto .P. Eaton, and R. Davies, "An examination of Single Event Functional Interrupts (SEFIs) in COTS SDRAMs," presented at 2006 SEE Symposium, Long-Beach, CA, Apr. 2006.
12. J. George, R. Koga, G. Swift, G. Allen, C. Carmichael, and C. W. Tseng, "Single Event Upsets in Xilinx Virtex-4 FPGA Devices," IEEE NSREC 2006 Data Workshop record, pp. 109-114.
13. Paul Graham, Heather Quinn, Jim Krone, Michael Caffrey, Sana Rezgui and Carl Carmichael, "Radiation-Induced Multi-bit Upsets in Xilinx SRAM-Based FPGAs," MAPLD, Washington DC, Sept. 2005
14. J.W. Howard, H. Kim, M. Berg, K.A. LaBel, et al. " Development of a Low Cost and High Speed Single Event Effects Tester based on Reconfigurable Field Programmable Gate Arrays (FPGA)," Presented at SEE Symposium 2006, Long Beach, Apr. 2006.
15. J. George, R. Koga, G. Swift, G. Allen, C. Cannicheal, and C.W. Tseng, "Single Event Upsets in Xilinx Virtex-4 FPGA Devices." IEEE NSREC 2006 Data Workshop record. pp 109-114
16. Christian Poivey, Melanie Berg, Kenneth A. LaBel, et al. "Single Event Effects (SEE) Response of Embedded Power PCs in a Xilinx Virtex-4 FPGA for a Space Application.", to be presented at RADECS 2007, Deauville, Sept. 2007