High-level optimization of integer multipliers over a finite bit-width with verification capabilities

2009 7th IEEE-ACM International Conference on Formal Methods and Models for Co-Design, MEMOCODE '09

Volumn , Issue , 2009, Pages 56-65

  Sarbishei, O ^a   Tabandeh, M ^a   Alizadeh, B ^b   Fujita, M ^b  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY REPRESENTATIONS; BIT-WIDTH; CARE OPTIMIZATION; CONVENTIONAL OPTIMIZATION; EFFICIENT ARCHITECTURE; LOGIC OPTIMIZATION; MULTIPLY-ACCUMULATOR UNITS; OPTIMIZATION APPROACH; RESIDUE NUMBER SYSTEM;

FORMAL METHODS; OPTIMIZATION; SIGNAL PROCESSING;

INTEGER PROGRAMMING;

EID: 70449501704     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2009.5185378     Document Type: Conference Paper

References (10)

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