Optimizing Residue arithmetic on FPGAs

Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008

Volumn , Issue , 2008, Pages 41-48

  Fu, Haohuan ^a   Mencer, Oskar ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM PROCESSORS; SIGNAL PROCESSING;

APPLICATION LEVELS; ARITHMETIC LIBRARIES; ARITHMETIC UNITS; BINARY NUMBERS; BIT WIDTHS; CHINESE REMAINDER THEOREMS; MODULI SETS; NOVEL DESIGNS; NUMBER REPRESENTATIONS; RESIDUE ARITHMETICS; RESIDUE NUMBER SYSTEMS; REVERSE CONVERTERS;

DESIGN;

EID: 63049124722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2008.4762364     Document Type: Conference Paper

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