Intellectual property protection for RNS circuits on FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 1139-1141

  Parrilla, Luis ^a   Castillo, Encarnación ^a   García, Antonio ^a   Lloris, Antonio ^a  

^a UNIVERSITY OF GRANADA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NUMBERING SYSTEMS; TIMING CIRCUITS;

CIC FILTERS; ELECTRONIC SIGNATURES; INTELLECTUAL PROPERTY PROTECTION; PROGRAMMABLE DEVICES; PROTECTION SCHEMES; RESIDUE NUMBER SYSTEM;

INTELLECTUAL PROPERTY;

EID: 34249827485     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_149     Document Type: Conference Paper

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