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Volumn , Issue , 2007, Pages 1131-1135

An efficient FPGA based MIMO-MMSE detector

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK RAMS; DYNAMIC SCALING; FPGA-BASED IMPLEMENTATION; GRAM-SCHMIDT; MIMO DETECTORS; MMSE DETECTION; MMSE DETECTORS; Q R DECOMPOSITION; SQUARE-ROOT; VLSI ARCHITECTURES;

EID: 70449466437     PISSN: 22195491     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (16)
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    • Paulraj, A.J.1    Gore, D.2    Nabar, R.U.3    Bolcskei, H.4
  • 4
    • 0026961023 scopus 로고
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    • C.M. Rader, "MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer scale integration", Application Specific Array Processors, 1992, Proceedings of the International Conference on, Aug. 1992
    • (1992) Application Specific Array Processors
    • Rader, C.M.1
  • 6
    • 0033708873 scopus 로고    scopus 로고
    • An efficient square-root algorithm for BLAST
    • ICASSP '00. Proceedings IEEE International Conference on
    • Babak Hassibi, "An Efficient Square-Root Algorithm for BLAST", Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE International Conference on
    • (2000) Acoustics, Speech, and Signal Processing, 2000
    • Hassibi, B.1
  • 7
    • 26944472832 scopus 로고    scopus 로고
    • Low complexity receiver design for MIMO bit-interleaved coded modulation
    • Sep
    • Iain B. Collings, Michael R.G. Butler and Matthew R. McKay, "Low Complexity Receiver Design for MIMO Bit-Interleaved Coded Modulation", ISSSTA2004, Sep, 2004.
    • (2004) ISSSTA2004
    • Collings, I.B.1    Butler, M.R.G.2    McKay, M.R.3
  • 8
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    • Conference Record of the Thirty-Ninth Asilomar Conference on
    • Markus Myllyla, Juha-Matti Hintikka, Joseph R. Cavallaro and Markku Juntti, "Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems", Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on
    • (2005) Signals, Systems and Computers
    • Myllyla, M.1    Hintikka, J.-M.2    Cavallaro, J.R.3    Juntti, M.4
  • 9
    • 34547365814 scopus 로고    scopus 로고
    • An efficient regular matrix inversion circuit architecture for MIMO processing
    • ISCAS 2006. Proceedings IEEE International Symposium on
    • Isabelle LaRoche, Sebatien Roy, "An Efficient Regular Matrix Inversion Circuit Architecture for MIMO Processing", Circuits and Systems, 2006. ISCAS 2006. Proceedings IEEE International Symposium on
    • (2006) Circuits and Systems
    • LaRoche, I.1    Roy, S.2
  • 10
    • 49149097777 scopus 로고    scopus 로고
    • A scalable pipelined complex valued matrix inversion architecture
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    • Fredrik Edman, Viktor Öwall, "A Scalable Pipelined Complex Valued Matrix Inversion Architecture", Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
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  • 11
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    • Signals, Systems and Computers, 2005
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  • 12
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.