|
Volumn , Issue , 2005, Pages 4489-4492
|
A scalable pipelined complex valued matrix inversion architecture
|
Author keywords
[No Author keywords available]
|
Indexed keywords
ARITHMETIC OPERATIONS;
CORE PROCESSORS;
GIVENS ROTATION;
HARDWARE IMPLEMENTATIONS;
HIGH THROUGHPUT;
LINEAR ARRAY ARCHITECTURE;
MATRIX INVERSIONS;
MATRIX MULTIPLICATION;
MODERN SIGNAL PROCESSING;
SCALABLE HARDWARE ARCHITECTURE;
SMART ANTENNA SYSTEMS;
THROUGHPUT RATE;
TRIANGULAR ARRAYS;
UPPER TRIANGULAR MATRICES;
ARCHITECTURE;
ARRAY PROCESSING;
COMPUTER ARCHITECTURE;
HARDWARE;
SIGNAL PROCESSING;
SMART ANTENNAS;
THROUGHPUT;
MATRIX ALGEBRA;
|
EID: 49149097777
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2005.1465629 Document Type: Conference Paper |
Times cited : (51)
|
References (13)
|