An efficient regular matrix inversion circuit architecture for MIMO processing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4819-4822

  LaRoche, Isabelle ^a   Roy, Sébastien ^a  

^a UNIVERSITÉ LAVAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMMUNICATION CHANNELS (INFORMATION THEORY); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ITERATIVE METHODS; MEAN SQUARE ERROR;

CLOCK FREQUENCY; MATRIX INVERSION CIRCUITS; MINIMUM MEAN-SQUARE ERROR PROCESSING;

ELECTRIC NETWORK ANALYSIS;

EID: 34547365814     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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