Testing embedded cores-based system-on-a-chip (SoC) - Test architecture and implementation

Proceedings of the IASTED International Conference on Modelling, Identification and Control

Volumn 23, Issue , 2004, Pages 300-306

  Das, Sunil R ^a,b   Assaf, Mansour H ^a   Petriu, Emil M ^a   Jin, Liwu ^a   Jin, Chuan ^a   Biswas, Dhruv ^a   Sahinoglu, Mehmet ^b  

^a UNIVERSITY OF OTTAWA   (Canada)

^b TROY UNIVERSITY   (United States)

Author keywords

Built in self test (BIST); IP core; Module under test (MUT); Response compaction unit (RCU); Space compression; System on a chip (SoC); Test pattern generator (TPG); Verilog VHDL

Indexed keywords

ALGORITHMS; AUTOMATION; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; COMPUTER SOFTWARE; DATA ACQUISITION; EMBEDDED SYSTEMS; PROBABILITY; PROBLEM SOLVING; STORAGE ALLOCATION (COMPUTER);

IP CORE; MODULE UNDER TEST (MUT); RESPONSE COMPACTION UNIT (RCU); SPACE COMPRESSION; SYSTEM-ON-A-CHIP (SOC); TEST PATTERN GENERATOR (TPG); VERILOG VHDL;

BUILT-IN SELF TEST;

EID: 7044271374     PISSN: 10258973     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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