Physical unclonable function and true random number generator: A compact and scalable implementation

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2009, Pages 425-428

  Maiti, Abhranil ^a   Nagesh, Raghunandan ^a   Reddy, Anand ^a   Schaumont, Patrick ^a  

^a State University   (United States)

Author keywords

FPGA; Jitter; Macro; PUF; Ring oscillators (RO); Scalable; TRNG

Indexed keywords

FPGA; PUF; RING OSCILLATORS (RO); SCALABLE; TRNG;

ACCESS CONTROL; CRYPTOGRAPHY; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); JITTER; LAKES; NUMBER THEORY; RANDOM NUMBER GENERATION;

OSCILLATORS (ELECTRONIC);

EID: 70350588743     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531542.1531639     Document Type: Conference Paper

References (10)

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