Extending an embedded RISC microprocessor for efficient translation based Java execution

Microprocessors and Microsystems

Volumn 33, Issue 7-8, 2009, Pages 415-429

  Sideris, Isidoros ^a   Pekmestzi, Kiamal ^a   Economakos, George ^a  

^a NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

Author keywords

Codesigned virtual machine; Embedded Java; Java processor

Indexed keywords

CODESIGNED VIRTUAL MACHINE; EMBEDDED APPLIANCES; EMBEDDED JAVA; EMBEDDED RISC PROCESSORS; HAND HELD DEVICE; JAVA EXECUTION; JAVA PROCESSOR; JAVA VIRTUAL MACHINES; OPERATING SYSTEMS; RISC MICROPROCESSORS; RISC PROCESSORS; SECURITY CHECKS; SET TOP BOX; SMART PHONES;

COMPUTER OPERATING SYSTEMS; EMBEDDED SYSTEMS; JAVA PROGRAMMING LANGUAGE;

REDUCED INSTRUCTION SET COMPUTING;

EID: 70350494722     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2009.06.003     Document Type: Article

References (34)

1. ARM Jazelle technology, .
2. Java solutions for embedded appliances, JTRON on picoJava II, .
3. JavaBenchEmbedded benchmarks pack, .
4. Jikes Research Virtual Machine, .
5. Nazomi JA 108 product brief, Available at .
6. Pendragon Software Corporation Caffeine Mark 3.0, .
7. PicoJava II FPGA implementation sources, .
8. PicoJava II FPGA implementation vs JOP, .
9. SandCraft SR1 microprocessor product brief, .
10. SimpleScalar LLC webpage, .
11. SPEC JVM98 Benchmark, .
12. Toshiba ARM product brief, .
13. picoJava-II Processor, Data Sheet, 1999.
14. Choquette J., Gupta M., McCarthy D., and Veenstra J. High-performance RISC microprocessors. IEEE Micro 19 4 (1999) 48-55
15. Cramer T., Friedman R., Miller T., Seberger D., Wilson R., and Wolczko M. Compiling Java just in time. IEEE Micro 17 3 (1997) 36-43
16. El-Kharashi M., Elguibaly F., and Li K. A robust stack folding approach for Java processors: an operand extraction-based algorithm. Journal of Systems Architecture 47 8 (2001) 697-726
17. El-Kharashi M.W., ElGuibaly F., and Li K.F. A quantitative study for Java microprocessor architectural requirements. Part I: instruction set design. Microprocessors and Microsystems 24 5 (2000) 225-236
18. El-Kharashi M.W., ElGuibaly F., and Li K.F. A quantitative study for Java microprocessor architectural requirements. Part II: high-level language support. Microprocessors and Microsystems 24 5 (2000) 237-250
19. M. Gschwind, Method and apparatus for determining branch addresses in programs generated by binary translation, IBM Technical Disclosure YOR8-1998-0334 (July 1998). URL citeseer.ist.psu.edu/gschwind98method.html.
20. Kim A., and Chang J.M. Java bytecode optimization with advanced instruction folding mechanism. ISHPC'00: Proceedings of the Third International Symposium on High Performance Computing (2000), Springer-Verlag, London, UK
21. H.-S. Kim, J. Smith, Dynamic binary translation for accumulator-oriented architectures, Code Generation and Optimization, 2003, CGO 2003, in: International Symposium on, 2003, pp. 25-35.
22. A. Klaiber, The technology behind crusoe processors, Tech. Rep., Transmeta Corporation (January 2000). URL http://www.transmeta.com/pdfs/paper_aklaiber_19jan00.pdf.
23. McGhan H., and O'Connor M. PicoJava: a direct execution engine for Java bytecode. Computer 31 10 (1998) 22-30
24. In: Narayanan V., and Wolczko M.I. (Eds). Java Microarchitectures (2002), Kluwer Academic Publishers, Norwell, MA, USA 1-18 Chap. 1
25. In: Narayanan V., and Wolczko M.I. (Eds). Java Microarchitectures (2002), Kluwer Academic Publishers, Norwell, MA, USA
26. C. Porthouse, Jazelle for execution environments, Available at http://www.arm.com (May 2005).
27. Puffitsch W., and Schoeberl M. picoJava-II in an FPGA. JTRES'07: Proceedings of the 5th International Workshop on Java Technologies for Real-Time and Embedded Systems (2007), ACM, New York, NY, USA
28. Schoeberl M. A Java processor architecture for embedded real-time systems. Journal of Systems Architecture 54 1-2 (2008) 265-286
29. Sideris I., Pekmestzi K., and Economakos G. A predecoding technique for ILP exploitation in Java processors. Journal of Systems Architecture 54 7 (2008) 707-728
30. Smith J.E., and Nair R. Virtual Machines - Versatile Platforms for Systems and Processes (2005), Morgan Kaufman
31. L. Su, M.H. Lipasti, Speculative optimization using hardware-monitored guarded regions for Java virtual machines, in: VEE, 2007.
32. Tan Y., Yiu L.W., Hang Y.C., Li R., and Fong A.S. A Java processor with hardware-support object-oriented instructions. Microprocessors and Microsystems 30 8 (2006) 469-479
33. J.-W. van de Waerdt, S. Vassiliadis, S. Das, S. Mirolo, C. Yen, B. Zhong, C. Basto, J.-P. van Itegem, D. Amirtharaj, K. Kalra, P. Rodriguez, H. van Antwerpen, The tm3270 media-processor, Microarchitecture, 2005. MICRO-38, in: Proceedings 38th Annual IEEE/ACM International Symposium on.
34. tm platforms on a 130-nm embedded processor core. IEICE Transactions 90-C 2 (2007) 523-530