Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 393-396

  Nakata, S ^a   Kusumoto, T ^b   Miyama, M ^b   Matsuda, Y ^b  

^a NTT CORPORATION   (Japan)

^b KANAZAWA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA PENALTY; BIT LINES; CELL LAYOUT; CURRENT FLOWS; ELECTROMIGRATION PROBLEMS; LINE VOLTAGE; MEMORY CELL; NMOSFET; POWER LINES;

ELECTRIC LINES; ELECTROMIGRATION; MOSFET DEVICES; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE; TELECOMMUNICATION LINES;

CELL MEMBRANES;

EID: 70350169807     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117768     Document Type: Conference Paper

References (6)

1. K. Zhang et al., "A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," in Proc. ISSCC Dig., pp.474-475, Feb. 2005.
2. M. Yamaoka et al., "Low-power embedded SRAM modules with expanding margins for writing," in Proc. ISSCC Dig., pp.480-481, Feb. 2005.
3. S. Ohbayashi et al., "A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits," in Proc. Symp. VLSI Circuits Dig., pp.17-18, June 2006.
4. S. Nakata, "Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage," IEICE Electron. Express, vol. 3, pp.304-309, July 2006.
5. 2," in Proc. IEEE Symp. Low Power Electronics Dig., pp.100-101, Oct. 1994.
6. S. Nakata, "Stability of adiabatic circuit using asymmetric 1D-capacitor array between the power supply and ground," IEICE Electron. Express, vol. 4, pp.165-171, Mar. 2007.