Sensitivity of output response to geometrical dimensions in VLSI interconnects

2009 IEEE Workshop on Signal Propagation on Interconnects, SPI '09

Volumn , Issue , 2009, Pages

  Ligocka Wardzińska, Agnieszka ^a   Bandurski, Wojciech ^a  

^a POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

GEOMETRICAL DIMENSIONS; MICROSTRIP MODELS; MULTIPLE SCALES METHODS; OUTPUT RESPONSE; RAMP RESPONSE; VLSI INTERCONNECTS;

INTERCHANGES; INTERCONNECTION NETWORKS;

SENSITIVITY ANALYSIS;

EID: 70350000413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPI.2009.5089863     Document Type: Conference Paper

References (6)

1. Cheng, Ch, Lillis, J, Lin, S, Chang, N, "Interconnect Analysis and Synthesis", Wiley & Sons, 2000.
2. Ismail Y.I, Friedman E.G., "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits", IEEE Tran. VLSI Sys., vol. 8, No. 2, April 2000, pp. 195-206
3. Deutsch A. et al., "When are transmission-line effects important for on-chip inerconnections", IEEE Tran.on MTT., vol. 45, No. 10, Octob.1997, pp. 1836-1846.
4. Kahng A.B., Muddu S., "An analytical delay model for RLC interconnects", IEEE Trans. on Computer-aided design of Integrated Circuits and Systems, Vol.16, Dec. 1997, pp.1507-1514.
5. Kang S.M. and Y. Leblebici "CMOS Digital Integrated Circuits: Analysis and Design" Third Edition, McGraw-Hill Publishing Co., New York, 2003.
6. Ligocka A., Bandurski, W., "Multiple Scales Method in Calculation of VLSI Interconnects Threshold Crossing Time", IEEE Trans. on Advanced Packaging, (to be published)