메뉴 건너뛰기




Volumn 5216 LNCS, Issue , 2008, Pages 141-152

On evolutionary synthesis of linear transforms in FPGA

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HEURISTIC METHODS;

EID: 70349858079     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-85857-7_13     Document Type: Conference Paper
Times cited : (18)

References (12)
  • 3
    • 0345872301 scopus 로고    scopus 로고
    • Evolutionary synthesis of arithmetic circuit structures
    • Aoki, T., Homma, N., Higuchi, T.: Evolutionary Synthesis of Arithmetic Circuit Structures. Artificial Intelligence Review 20(3-4), 199-232 (2003
    • (2003) Artificial Intelligence Review , vol.20 , Issue.3-4 , pp. 199-232
    • Aoki, T.1    Homma, N.2    Higuchi, T.3
  • 5
    • 33746265840 scopus 로고    scopus 로고
    • Automatic discovery of RTL benchmark circuits with predefined testability properties
    • IEEE Computer Society, Los Alamitos
    • Pecenka, T., Kotasek, Z., Sekanina, L., Strnadel, J.: Automatic discovery of RTL benchmark circuits with predefined testability properties. In: 2005 NASA / DoD Conference on Evolvable Hardware, pp. 51-58. IEEE Computer Society, Los Alamitos (2005
    • 2005 NASA / DoD Conference on Evolvable Hardware , vol.2005 , pp. 51-58
    • Pecenka, T.1    Kotasek, Z.2    Sekanina, L.3    Strnadel, J.4
  • 7
    • 84937417817 scopus 로고    scopus 로고
    • An evolutionary approach to automatic generation of VHDL code for low-power digital filters
    • Miller, J., Tomassini, M., Lanzi, P.L., Ryan, C., Tetamanzi, A.G.B., Langdon, W.B. (eds. Springer, Heidelberg
    • Erba, M., Rossi, R., Liberali, V., Tettamanzi, A.: An evolutionary approach to automatic generation of VHDL code for low-power digital filters. In: Miller, J., Tomassini, M., Lanzi, P.L., Ryan, C., Tetamanzi, A.G.B., Langdon, W.B. (eds.) EuroGP 2001. LNCS, vol.2038, pp. 36-50. Springer, Heidelberg (2001
    • (2001) EuroGP 2001. LNCS , vol.2038 , pp. 36-50
    • Erba, M.1    Rossi, R.2    Liberali, V.3    Tettamanzi, A.4
  • 8
    • 25844438473 scopus 로고    scopus 로고
    • Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform
    • Hounsell, B.I., Arslan, T., Thomson, R.: Evolutionary design and adaptation of high performance digital filters within an embedded reconfigurable fault tolerant hardware platform. Soft Computing 8(5), 307-317 (2004
    • (2004) Soft Computing , vol.8 , Issue.5 , pp. 307-317
    • Hounsell, B.I.1    Arslan, T.2    Thomson, R.3
  • 9
    • 11244264495 scopus 로고    scopus 로고
    • Multiplier block synthesis using evolutionary graph generation
    • IEEE Computer Society Press, Los Alamitos
    • Homma, N., Aoki, T., Higuchi, T.: Multiplier block synthesis using evolutionary graph generation. In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), pp. 79-82. IEEE Computer Society Press, Los Alamitos (2004
    • (2004) 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004) , pp. 79-82
    • Homma, N.1    Aoki, T.2    Higuchi, T.3
  • 10
    • 34250199345 scopus 로고    scopus 로고
    • Multiplierless multiple constant multiplication
    • Voronenko, Y., Puschel, M.: Multiplierless multiple constant multiplication. ACM Transactions on Algorithms 3(2), 1-282 (2007
    • (2007) ACM Transactions on Algorithms , vol.3 , Issue.2 , pp. 1-282
    • Voronenko, Y.1    Puschel, M.2
  • 11
    • 84956996977 scopus 로고    scopus 로고
    • Virtual reconfigurable circuits for real-world applications of evolvable hardware
    • Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds. Springer, Heidelberg
    • Sekanina, L.: Virtual reconfigurable circuits for real-world applications of evolvable hardware. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol.2606, pp. 186-197. Springer, Heidelberg (2003
    • (2003) ICES 2003. LNCS , vol.2606 , pp. 186-197
    • Sekanina, L.1
  • 12
    • 0001784339 scopus 로고    scopus 로고
    • A high-performance, pipelined, FPGA-based genetic algorithm machine
    • Shackleford, B.: A high-performance, pipelined, FPGA-based genetic algorithm machine. Genetic Programming and Evolvable Machines 2(1), 33-60 (2001
    • (2001) Genetic Programming and Evolvable Machines , vol.2 , Issue.1 , pp. 33-60
    • Shackleford, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.