Multiplier block synthesis using evolutionary graph generation

Proceedings - 2004 NASA/DoD Conference on Evolvable Hardware

Volumn , Issue , 2004, Pages 79-82

  Homma, Naofumi ^a   Aoki, Takafumi ^a   Higuchi, Tatsuo ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b TOHOKU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC CIRCUITS; EVOLUTIONARY GRAPH GENERATION (EGG); GENETIC PROGRAMMING (GP); HIERARCHICAL SYNTHESIS;

COMPUTER PROGRAMMING; CONSTRAINT THEORY; DATA REDUCTION; ELECTRIC NETWORK ANALYSIS; ELECTRON MULTIPLIERS; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; RAW MATERIALS; TREES (MATHEMATICS);

GRAPHIC METHODS;

EID: 11244264495     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.2004.1310812     Document Type: Conference Paper

References (9)

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8. R. I. Hartley, "Subexpression sharing in filters using canonic signed digit multipliers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, pp. 677 - 688, Oct. 1996.
9. N. Homma, "Evolutionary graph generation system and its application to circuit synthesis," Doctoral dissertation, Tohoku University, Aug. 2001.