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Volumn , Issue , 2009, Pages 104-113

Analysis of photonic networks for a chip multiprocessor using scientific applications

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CHIP MULTIPROCESSOR; CMOS TECHNOLOGY; COMMUNICATION PATTERN; COMPARATIVE ANALYSIS; CYCLE ACCURATE; ELECTRONIC NETWORKS; HIGH ENERGY CONSUMPTION; HYBRID NETWORK; MAPPING METHOD; OMNET++; PHOTONIC NETWORK; REAL APPLICATIONS; SCIENTIFIC APPLICATIONS; SYNTHETIC BENCHMARK;

EID: 70349836053     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2009.5071458     Document Type: Conference Paper
Times cited : (50)

References (22)
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    • Canning, A.1    Wang, L.2    Williamson, A.3    Zunger, A.4
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    • 70349818046 scopus 로고    scopus 로고
    • The international technology roadmap for semiconductors ITRS
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  • 12
    • 60449108891 scopus 로고    scopus 로고
    • High-speed 2×2 switch for multi-wavelength message routing in on-chip silicon photonic networks
    • Sept
    • B. G. Lee et al. High-speed 2×2 switch for multi-wavelength message routing in on-chip silicon photonic networks. In European Conference on Optical Communication (ECOC), Sept. 2008.
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    • Lee, B.G.1
  • 13
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    • Lin, Z.1    Ethier, S.2    Hahm, T.3    Tang, W.4
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    • Photonic networks-on-chip for future generations of chip multiprocessors
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    • Shacham, A.1    Bergman, K.2    Carloni, L.P.3
  • 20
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    • High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks
    • April
    • Y. Vlasov, W.M.J. Green, and E. Xia. High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks. Nature Photonics, 2:242-246, April 2008.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.