A parallel decoding algorithm of LDPC codes using CUDA

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2008, Pages 171-175

  Wang, Shuang ^a   Cheng, Samuel ^a   Wu, Qiang ^b  

^a UNIVERSITY OF OKLAHOMA TULSA   (United States)

^b Soft Imaging LLC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BELIEF PROPAGATION ALGORITHM; CO-PROCESSORS; COMPUTE UNIFIED DEVICE ARCHITECTURES; HARDWARE AND SOFTWARE; HIGH MEMORY BANDWIDTH; LDPC CODES; LOW-DENSITY PARITY-CHECK CODES; MULTITHREADED; PARALLEL DATA; PARALLEL DECODING ALGORITHM;

DECODING; SOFTWARE ARCHITECTURE;

PARALLEL ALGORITHMS;

EID: 70349667400     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2008.5074385     Document Type: Conference Paper

References (13)

1. R. G Gallager, "Low-Density Parity-Check Codes," IRE Trans. Inform. Theory, voL IT-8, pp. 21-28, Jan. 1962.
2. R. G Gallager, "Low-Density Parity-Check Codes," MTT Press, Cambridge, MA, 1963.
3. D. J. C. MacKay and Radford M. Neal, Near "Shannon Limit Performance of Low Density Parity Check Codes", Electronics Letters, voL 32, pp. 1645-1646, July 1996.
4. F. R. Kschischang, B. J. Frey, and H. A. Loeliger, "Factor graphs and the sum-product algorithm", IEEE Transactions on Information Theory, voL 47, pp. 498-519, Feb 2001.
5. C. Howland, A Blanksby, "Parallel decoding architectures for low density parity check codes", The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001. vol. 4, pp. 742 - 745, May 2001
6. K. Shimizu, T. Ishikawa, et al, "A parallel LSI architecture for LDPC decoder improving message-passing schedule", Proceedings. 2006 IEEE International Symposium on Circuits and Systems, 2006. ISCAS 2006. pp. 5099-5102, May 2006
7. Oh. Daesun, K.K Parhi, "Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes", IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007. pp. 1855 -1858, May 2007.
8. Nyland, Lars, Mark Harris, and Jan Prins. 2004. "The Rapid Evaluation of Potential Fields Using Programmable Graphics Hardware." Poster presentation at GP2, the ACM Workshop on General Purpose Computing on Graphics Hardware.
9. NVIDIA Corporation. 2007. NVIDIA CUDA Compute Unified Device Architecture Programming Guide. Version 1.1. http://www.nvidia.com/ objectfcuda-develop.html
10. P. Warden. Pete's GPU Notes, 2005. http://petewarden.com/notes/archives/ 2005/05/
11. William R Mark, R Steven Glanville, Kurt Akeley, Mark J. Kilgard, "Cg: A System for Programming Graphics Hardware in a C-like Language", Proceedings of SIGGRAPH 2003.
12. Shams, Ramtin; Barnes, Nick, "Speeding up Mutual Information Computation Using NVIDIA CUDA Hardware" 9th Biennial Conference of the Australian Pattern Recognition Society on Digital Image Computing Techniques and Applications, pp. 555-560, Dec. 2007
13. M.J. Bernhard "LDPC Codes - a brief Tutorial", http://users.tkk.fi/~pat/ coding/essays/ ldpc.pdf