Fused floating-point arithmetic for DSP

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2008, Pages 767-771

  Swartzlander Jr , Earl E ^a   Saleh, Hani H ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUTTERFLY OPERATION; BUTTERFLY UNIT; COMPLEX ADDITION; FLOATING POINT OPERATIONS; FLOATING-POINT ADDER; FLOATING-POINT ARITHMETIC; INNER PRODUCT; NUMERICAL RESULTS; RADIX 2; ROUNDING OPERATION;

ADDERS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSORS;

FAST FOURIER TRANSFORMS;

EID: 70349662048     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2008.5074512     Document Type: Conference Paper

References (13)

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