NoC power optimization using a reconfigurable router

Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Volumn , Issue , 2009, Pages 235-240

  Concatto, Caroline ^a   Matos, Debora ^a   Carro, Luigi ^a   Kastensmidt, Fernanda ^a   Susin, Altamiro ^a   Kreutz, Marcio ^b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b UNIVERSITY OF SANTA CRUZ DO SUL   (Brazil)

Author keywords

FIFO; Latency; Network on chip; Power dissipation; Reconfigurable router

Indexed keywords

FIFO; LATENCY; NETWORK-ON-CHIP; POWER DISSIPATION; RECONFIGURABLE ROUTER;

ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION;

ROUTERS;

EID: 70349656945     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2009.7     Document Type: Conference Paper

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