A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 56-57

  Yoo, Kwisung ^a   Lee, Dongmyung ^a   Han, Gunhee ^a   Park, Sung Min ^b   Oh, Won Seok ^c  

^a Yonsei University   (South Korea)

^b Ewha Womans University   (South Korea)

^c Korea Electronic Technology Institute (KETI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE; ENERGY DISSIPATION; GAIN CONTROL;

NEGATIVE-IMPEDANCE COMPENSATION TECHNIQUES; PROTECTION DIODES;

AMPLIFIERS (ELECTRONIC);

EID: 34548849100     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373585     Document Type: Conference Paper

References (4)

1. W. Z. Chen and C. H. Lu, "A 2.5Gbps CMOS Optical Receiver Analog Front-End," Proc. CICC, pp. 359-362, May, 2002.
2. E. Sackingor and W. C. Fischer, "A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 Receivers," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1884-1888, Dec., 2000.
3. S. Galal and B. Razavi, "10Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 188-189, Fob., 2003.
4. K. Yoo, G. Han, and S. M. Park, "A 5.1mW, 2.5Gb/s Limiting Amplifier for Optical Communications," Proc. IEEE ICECS, Dec., 2006.