A 2.5Gb/s ESD-protected dual-channel optical transceiver array

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 156-159

  Han, Jungwon ^a   Choi, Booyoung ^a   Park, Kangyeob ^b   Oh, Won Seok ^b   Park, Sung Min ^a  

^a Ewha Womans University   (South Korea)

^b Korea Electronic Technology Institute (KETI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL PLANTS; COMPUTER NETWORKS; TRANSCEIVERS;

DUAL CHANNELS; OPTICAL TRANSCEIVERS; SOLID-STATE CIRCUITS CONFERENCE;

CMOS INTEGRATED CIRCUITS;

EID: 51349084673     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425754     Document Type: Conference Paper

References (4)

1. B. -Y. Choi et al., "A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects", IEEE Proc. of ISCAS, pp. 181-184, May 2007.
2. Q. Le et al., "A Burst-Mode Receiver for 1.25-Gb/s Ethernet PON With AGC and Internally Created Reset Signal", IEEE J. of Solid-State Circuits, Vol. 39, pp. 2379-2388, Dec. 2004.
3. W. -Z. Chen et al., "A 1.8-V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-End" IEEE J. of Solid-State Circuits, Vol. 40, pp. 1388-1396, Jun. 2005.
4. C. -M. Tsai et al., "A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation", IEEE ISSCC Tech. Digest, pp. 52-53, Feb. 2007.