A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Tanaka, Nagataka ^a   Naruse, Junji ^a   Mori, Akiko ^a   Okamoto, Ryuta ^a   Yamashita, Hirofumi ^a   Monoi, Makoto ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349286691     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977299     Document Type: Conference Paper

References (5)

1. M. Mori et al., "A 1/4in 2M Pixel CMOS Image Sensor with 1.75Transistor/Pixel," ISSCC Dig. Tech. Papers, pp. 110-111, Feb. 2004.
2. K. Mabuchi et al., "CMOS Image Sensor Using a Floating Diffusion Driving Buried Photodiode," ISSCC Dig. Tech. Papers, pp. 112-113, Feb. 2004.
3. R.D. McGrath et al., "Shared Pixels for CMOS Image Sensor Arrays," IEEE Workshop on CCDs and Advanced Image Sensors, pp. 9-12, 2005.
4. B. Kim et al., "Gr Gb Difference in 3M CMOS Image Sensor with 1.75μm Pixel," Int. Image Sensor Workshop, pp. 271-274, 2007.
5. W. Lee et al., "A High S/N Ratio and High Full Well Capacity CMOS Image Sensor with Active Pixel Readout Feedback Operation," Asian Solid-State Circuits Conf., pp. 260-263, Nov. 2007.