APRON: A cellular processor array simulation and hardware design tool

Eurasip Journal on Advances in Signal Processing

Volumn 2009, Issue , 2009, Pages

  Barr, David R W ^a   Dudek, Piotr ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR PROCESSOR ARRAY; DEVELOPMENT ENVIRONMENT; EFFICIENT SIMULATION; HARDWARE ARCHITECTURE; HARDWARE DESIGN; PROCESSING HARDWARE; PROCESSOR ARRAY; SOFTWARE ENVIRONMENTS; SOFTWARE PROCESSOR; SOFTWARE USE; VISION CHIPS;

ARCHITECTURAL DESIGN; CELLULAR ARRAYS; GRAPHICAL USER INTERFACES; MULTILAYER NEURAL NETWORKS; PARALLEL ALGORITHMS; PROGRAM COMPILERS; PULSE AMPLIFIERS;

COMPUTER ARCHITECTURE;

EID: 68949085053     PISSN: 16876172     EISSN: 16876180     Source Type: Journal    
DOI: 10.1155/2009/751687     Document Type: Article

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