A novel method to analyze and design a NWL scheme dram

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2008, Pages 701-702

  Park, Seokhan ^a   Sung, Bonggu ^a   Jung, Hyuckchai ^a   Lim, Junhee ^a   Lee, Sangwoon ^a   Lee, Jooyoung ^a   Yang, Wonsuk ^a   Oh, Kyungseok ^a   Chung, Taeyoung ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 51549116309     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558996     Document Type: Conference Paper

References (4)

1. T. Hamamoto et al., "On the retention time distribution of dynamic random access memory (DRAM)" IEEE Trans. Electron Devices, vol.45, pp. 1300-1309, 1998.
2. J. Y. Kim et al., "The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond" in VLSI Technical Digest, pp.11-12, 2003.
3. M. Chang et al., "Impact of Gate-Induce Drain Leakage on Retention Time Distribution of 256Mbit DRAM With Negative word line Bias" in IEEE Trans. Electron Devices, vol.50, pp.1036-1041, 2003.
4. K. Saino et al., "Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time" in IEDM Tech. Dig., pp. 837-840, 2000.