Advanced SOI CMOS transistor technology for high performance microprocessors

Proceedings of the 10th International Conference on ULtimate Integration of Silicon, ULIS 2009

Volumn , Issue , 2009, Pages 11-14

  Horstmann, M ^a   Wiatr, M ^a   Wei, A ^a   Hoentschel, J ^a   Feudel, Th ^a   Scheiper, Th ^a   Stephan, R ^a   Gerhadt, M ^a   Raab, M ^a  

^a GLOBALFOUNDRIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TRANSISTORS; DESIGN RULES; DRESDENS; FIGURE OF MERIT; HIGH-PERFORMANCE MICROPROCESSORS; METAL GATE; POWER EFFICIENT; SILICON ON INSULATOR; SOI CMOS; STRAINED SI TECHNOLOGY; STRAINED SILICON; STRAINED-SI; TECHNOLOGY ELEMENT; TRANSISTOR SCALING; VOLUME MANUFACTURING;

INTEGRATION; MICROPROCESSOR CHIPS; TECHNOLOGY; TRANSISTORS;

SILICON;

EID: 67650679325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ULIS.2009.4897527     Document Type: Conference Paper

References (6)

1. M. Horstmann et al., Mat. Science and Eng. B (2004), 114-115, pp, 3-8
2. K. Mistry et al., IEDM 2007, p. 247
3. M. Horstmann et al., IEDM 2005 p. 243
4. S. Mantl et al., ISDRS, 2007 p. 1-2
5. J. Hoentschel et al., IEDM 2008 p. 649
6. A. Wei et al., VLSI 2007, p. 216