Sub-50 nm gate length SOI transistor development for high performance microprocessors

Materials Science and Engineering: B

Volumn 114-115, Issue SPEC. ISS., 2004, Pages 3-8

  Horstmann, M ^a   Greenlaw, D ^a   Feudel, Th ^a   Wei, A ^a   Frohberg, K ^a   Burbach, G ^a   Gerhardt, M ^a   Lenski, M ^a   Stephan, R ^a   Wieczorek, K ^a   Schaller, M ^a   Hohage, J ^a   Ruelke, H ^a   Klais, J ^a   Huebler, P ^a   Luning, S ^a   Van Bentum, R ^a   Grasshoff, G ^a   Schwan, C ^a   Cheek, J ^b   Buller, J ^b   Krishnan, S ^b   Raab, M ^a   Kepler, N ^b   more..

^a IBM MICROELECTRONICS   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

LGATE scaling; Partial depleted SOI technologies; Shallow trench isolation

Indexed keywords

ELECTRIC INVERTERS; MICROPROCESSOR CHIPS; OPTIMIZATION; OSCILLATORS (ELECTRONIC); SILICON ON INSULATOR TECHNOLOGY; STRAIN;

GATE LENGTH; LGATE SCALING; PARTIAL DEPLETED SOI TECHNOLOGIES; SHALLOW TRENCH ISOLATION;

TRANSISTORS;

EID: 10644256509     PISSN: 09215107     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mseb.2004.07.077     Document Type: Conference Paper

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