OCEANS: Optimizing compilers for embedded applications

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1300 LNCS, Issue , 1997, Pages 1351-1356

  Aarts, Bas ^a   Barreteau, Michel ^b   Bodin, François ^c   Brinkhaus, Peter ^d   Chamski, Zbigniew ^c   Charles, Henri Pierre ^b   Eisenbeis, Christine ^e   Gurd, John ^f   Hoogerbrugge, Jan ^a   Hu, Ping ^e   Jalby, William ^b   Knijnenburg, Peter M W ^d   O'Boyle, Michael F P ^g   Rohou, Erven ^c   Sakellariou, Rizos ^f   Schepers, Henk ^a   Seznec, André ^c   Stöhr, Elena ^f   Verhoeven, Marco ^a   Wijshoff, Harry A G ^d  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b UNIVERSITY OF VERSAILLES   (France)

^c CAMPUS DE BEAULIEU   (France)

^d LEIDEN UNIVERSITY   (Netherlands)

^e INRIA ROCQUENCOURT   (France)

^f UNIVERSITY OF MANCHESTER   (United Kingdom)

^g UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL PROCESSING SYSTEMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EMBEDDED APPLICATION; ITS APPLICATIONS; OPTIMIZING COMPILERS; PHILIPS; UNIT COST; VLIW PROCESSOR;

PROGRAM COMPILERS;

EID: 84878632280     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0002894     Document Type: Conference Paper

References (10)

1. G. Araujo et al. Challenges in Code Generation for Embedded Processors. In Code Generation for Embedded Processors. Kluwer Academic Publishers, pp. 49-64, 1995.
2. A. J. C. Bik, H. A. G. Wijshoff. MT1; A Prototype Restructuring Compiler. Technical Report 93-32, Department of Computer Science, Leiden University, Oct. 1993.
3. S. Carr, K. Kennedy. Improving the ratio of memory operation to floating-point operations in loops. ACM ToPLaS, 16(6), Nov. 1994, pp. 1768-1810.
4. S. Carr. Combining Optimizations for Cache and Instruction-Level Parallelism. Proceedings of PACT'96.
5. B. Case. Philips Hope to Displace DSPs with VLIW. Microprocessor Report, 8(16), 5 Dec. 1994, pp. 12-15.
6. See also http://www.trimedia-philips.com/
7. C. Eisenbeis, S. Lelait, B. Marmol. The meeting graph: a new model for loop cyclic register allocation. Proceedings of PACT'95.
8. E. Rohou, F. Bodin, A. Seznec, G. Le Fol, F. Charot, F. Raimbault. SALTO: System for Assembly-Language Transformation and Optimization. Technical Report 1032, IRISA, June 1996.
9. See also http://www.irisa.fr/caps
10. J. Wang, C. Eisenbeis, M. Jourdan, B. Su. Decomposed Software Pipelining: a New Perspective and a New Approach. International Journal on Parallel Processing, 22(3), 1994, pp. 357-379.