Evaluating resistance of MCML technology to power analysis attacks using a simulation-based methodology

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5430 LNCS, Issue , 2009, Pages 230-243

  Regazzoni, Francesco ^a   Eisenbarth, Thomas ^b   Poschmann, Axel ^b   Großschädl, Johann ^c   Gurkaynak, Frank ^d   Macchetti, Marco ^e   Toprak, Zeynep ^f   Pozzi, Laura ^a   Paar, Christof ^b   Leblebici, Yusuf ^f   Ienne, Paolo ^f  

^a UNIVERSITY OF LUGANO   (Switzerland)

^b RUHR UNIVERSITY BOCHUM   (Germany)

^c UNIVERSITY OF BRISTOL   (United Kingdom)

^d ETH ZURICH   (Switzerland)

^e Nagracard SA   (Switzerland)

^f EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

AES ALGORITHMS; CRYPTOGRAPHIC HARDWARE; DIFFERENTIAL POWER ANALYSIS; FULL-CORE; INPUT SIGNAL; LOGIC STYLE; MOS CURRENT-MODE LOGIC; POWER ANALYSIS ATTACK; POWER CONSUMPTION; POWER PROFILE; POWER TRACES; SIDE CHANNEL ATTACK; SIMULATION-BASED;

ELECTRIC POWER UTILIZATION;

EID: 67650295998     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-01004-0_13     Document Type: Conference Paper

References (15)

1. [AAE02] Anis, M., Allam, M., Elmasry, M.: Impact of technology scaling on CMOS logic styles. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] 49(8), 577-588 (2000) (Pubitemid 30910487)
2. [BCO04] Brier, ́E., Clavier, C., Olivier, F.: Correlation power analysis with a leakage model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol.3156, pp. 16-29. Springer, Heidelberg (2004) (Pubitemid 39112454)
3. [BGI+08] Badel, S., Guleyupoglu, E., Inac, O., Martinez, A.P., Vietti, P., Gurkaynak, F., Leblebici, Y.: A Generic Standard Cell Design Methodology for Differential Circuit Styles. In: Design Automation and Test in Europe 2008, pp. 843-848 (2008)
4. [BGLT04] Bucci, M., Guglielmo, M., Luzzi, R., Trifiletti, A.: A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol.3254, pp. 481-490. Springer, Heidelberg (2004) (Pubitemid 39744654)
5. [BS97] Biham, E., Shamir, A.: Differential fault analysis of secret key cryptosystems. In: Kaliski Jr., B.S. (ed.) CRYPTO 1997. LNCS, vol.1294, pp. 513-525. Springer, Heidelberg (1997) (Pubitemid 127112576)
6. [GR99] Gonzalez, J.L., Rubio, A.: Low delta-I noise CMOS circuits based on differential logic and current limiters. Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on [see also Circuits and Systems I: Regular Papers, IEEE Transactions on] 46(7), 872-876 (1999)
7. [IoSTN01] National Institute of Standards and Technology (NIST). Announcing the AdVanced Encryption Standard (AES). Federal Information Processing Standards Publication 197 (November 2001)
8. [KJJ99] Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol.1666, pp. 388-397. Springer, Heidelberg (1999)
9. [Koc96] Kocher, P.C.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol.1109, pp. 104-113. Springer, Heidelberg (1996) (Pubitemid 126106234)
10. [MKA92] Maskai, S.R., Kiaei, S., Allstot, D.J.: Synthesis techniques for CMOS folded source-coupled logic circuits. IEEE Journal of Solid-State Circuits 27(8), 1157-1167 (1992)
11. [MOP07] Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks: Revealing the Secrets of Smart Cards. AdVances in Information Security. Springer, Heidelberg (2007)
12. [RBE+07] Regazzoni, F., Badel, S., Eisenbarth, T., Großscädl, J., Poschmann, A., Toprak, Z., Macchetti, M., Pozzi, L., Paar, C., Leblebici, Y., Ienne, P.: A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. In: International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VII (2007)
13. [TAV02] Tiri, K., Akmal, M., Verbauwhede, I.M.: A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In: Proceedings of the 28th European Solid-State Circuits Conference (ESSCIRC 2002), September 2002, pp. 403-406. University of Bologna, Bologna (2002)
14. [TAY+05] Toprak, Z., Verma, A., Leblebici, Y., Ienne, P., Paar, C.: Design of Low- Power DPA-Resistant Cryptographic Functional Units. In: Workshop on Cryptographic AdVances in Secure Hardware (2005)
15. [TV03] Tiri, K., Verbauwhede, I.: Securing encryption algorithms against DPA at the logic level: Next generation smart card technology. In: Walter, C.D., Ko̧c, Ç .K., Paar, C. (eds.) CHES 2003. LNCS, vol.2779, pp. 125-136. Springer, Heidelberg (2003) (Pubitemid 37171083)