Low delta-I noise CMOS circuits based on differential logic and current limiters

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 46, Issue 7, 1999, Pages 872-876

  Gonzalez, Jose Luis ^a   Rubio, Antonio ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LIMITERS; SPURIOUS SIGNAL NOISE;

DIFFERENTIAL LOGIC; SELF TIME LOGICS; SWITCHING NOISE;

COMBINATORIAL CIRCUITS;

EID: 0032641423     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.774239     Document Type: Article

References (7)

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