A 500-MHz MRAM macro for high-performance SoCs

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 261-264

  Sakimura, Noboru ^a   Nebashi, Ryusuke ^a   Honjo, Hiroaki ^a   Saito, Shinsaku ^a   Kato, Yuko ^a   Sugibayashi, Tadahiko ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS TIME; BIT LINES; CELL-BASED; CMOS PROCESS; MAGNETIC TUNNEL JUNCTION; OPERATION SPEED; PRE-CHARGE;

RANDOM ACCESS STORAGE; SEMICONDUCTOR JUNCTIONS; TUNNEL JUNCTIONS;

MAGNETIC STORAGE;

EID: 67649980229     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708778     Document Type: Conference Paper

References (4)

1. N. Sakimura, et al.,"MRAM Cell Technology for Over 500-MHz SoC," Journal of Solid State Circuits, vol. 42, no. 4, pp830-838, April 2007.
2. N. Sakimura, et al.,"A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture," in A-SSCCDig. Tech. Papers, pp. 216-219, Nov. 2007.
3. R. Nebashi, et al.,"A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme," in A-SSCCDig. Tech. Papers, pp. 220-223, Nov. 2007.
4. H. Honjo, et al.,"Performance of write-line inserted MTJ for low-write-current MRAM cell," Journal of Applied Physics 103,07A711, 2008.