A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 220-223

  Nebashi, Ryusuke ^a   Sakimura, Noboru ^a   Sugibayashi, Tadahiko ^a   Kasai, Naoki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; MAGNETIC STORAGE; RANDOM ACCESS STORAGE; SPICE;

ACCESS TIME; CELL ARRAYS; SOLID-STATE CIRCUITS CONFERENCE;

CYTOLOGY;

EID: 51349128758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425770     Document Type: Conference Paper

References (6)

1. N. Sakimura et al., IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 830-838, Apr. 2007.
2. N Sakimura et al., ISSCC Digest of Technical Papers, pp. 278-279, 2003.
3. Y. Asao et al., IEDM Technical Digest, pp. 571-574, 2004.
4. T. Y. Kim et al., A-SSCC, pp. 117-120, Nov. 2005.
5. H. Tanizaki et al., A-SSCC, pp. 303-306, 2006.
6. Numata, et al. to be presented in VLSI symposia, 2007.