Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

Journal of China Universities of Posts and Telecommunications

Volumn 16, Issue 3, 2009, Pages 89-94

  LI, Zhen rong ^a   ZHUANG, Yi qi ^a   ZHANG, Chao ^a   JIN, Gang ^a  

^a XIDIAN UNIVERSITY   (China)

Author keywords

AES; application specific integrated circuit (ASIC); architecture; decryption; encryption; Zigbee

Indexed keywords

AES; APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC); DECRYPTION; ENCRYPTION; ZIGBEE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARCHITECTURAL DESIGN; CHARGE COUPLED DEVICES; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; INTEGRATED CIRCUITS; METALLIC COMPOUNDS; MICROPROCESSOR CHIPS; MOS DEVICES;

CRYPTOGRAPHY;

EID: 67649210823     PISSN: 10058885     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1005-8885(08)60232-0     Document Type: Article

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