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Volumn , Issue , 2007, Pages 353-356

Implementations of high throughput sequential and fully pipelined AES processors on FPGA

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COST EFFECTIVENESS; DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MATHEMATICAL TRANSFORMATIONS; PROGRAM PROCESSORS;

EID: 43749110679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPACS.2007.4445896     Document Type: Conference Paper
Times cited : (30)

References (11)
  • 1
    • 85177116455 scopus 로고    scopus 로고
    • Advanced Encryption Standard (AES) 2001
    • (2001)
  • 2
    • 85177108780 scopus 로고    scopus 로고
  • 3
    • 85177113611 scopus 로고    scopus 로고
    • J. Hyoung Shim D. Won Kim K. Young T. Won Kwon J. Rim Choi A Rijndael cryptoprocessor using shared on-the-fly key scheduler IEEE Asia-Pacific Conference on ASIC 89 92 2002
    • (2002) , pp. 89-92
  • 4
    • 85177107250 scopus 로고    scopus 로고
    • R. Sever A.N. Ismailglu Y.C. Tekmen M. Askar B. Okcan A high speed FPGA implementation of the Rijndael algorithm Euromicro Symposium on Digital System Design 358 362 2004
    • (2004) , pp. 358-362
  • 5
    • 0036933530 scopus 로고    scopus 로고
    • Architectures and VLSI implementations of the AES-Proposal Rijndael
    • N. Sklavos O. Koufopavlou Architectures and VLSI implementations of the AES-Proposal Rijndael EEEE Transactions on Computers 51 12 1454 1459 2002
    • (2002) EEEE Transactions on Computers , vol.51 , Issue.12 , pp. 1454-1459
  • 6
    • 85177124796 scopus 로고    scopus 로고
  • 7
    • 85177119246 scopus 로고    scopus 로고
    • N.A. Saqib F. Rodriguez-Henriquez A. Diaz-Perez AES algorithm implementation-an efficient approach for sequential and pipeline architectures the Fourth Mexican International Conference on Computer Science 126 130 2003
    • (2003) , pp. 126-130
  • 8
    • 85177114172 scopus 로고    scopus 로고
  • 9
    • 85177128047 scopus 로고    scopus 로고
    • D. Kotturi S. Moo Yoo J. Blizzard AES crypto chip utilizing high-speed parallel pipelined architecture IEEE International Symposium on Circuits and Systems 5 4653 4656 2005
    • (2005) , vol.5 , pp. 4653-4656
  • 10
    • 85177125044 scopus 로고    scopus 로고
    • A. Hodjat I. Verbauwhede A 21.54 Gbits/s fully pipelined AES processor on FPGA 12 Annual IEEE Symposium on Field-Programmable Custom Computing Machines 308 309 2004
    • (2004) , pp. 308-309
  • 11
    • 4544352628 scopus 로고    scopus 로고
    • High-speed VLSI architectures for the AES algorithm
    • X. Zhang K.K. Parhi High-speed VLSI architectures for the AES algorithm IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 9 957 967 2004
    • (2004) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.12 , Issue.9 , pp. 957-967


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.