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Volumn , Issue , 2007, Pages 353-356
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Implementations of high throughput sequential and fully pipelined AES processors on FPGA
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
COST EFFECTIVENESS;
DATA STORAGE EQUIPMENT;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
MATHEMATICAL TRANSFORMATIONS;
PROGRAM PROCESSORS;
FUNCTIONAL BLOCKS;
HARDWARE SHARING;
MICROPROCESSOR CHIPS;
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EID: 43749110679
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISPACS.2007.4445896 Document Type: Conference Paper |
Times cited : (30)
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References (11)
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