SCOPUS 정보 검색 플랫폼

Microsystem Technologies

Volumn 15, Issue 8, 2009, Pages 1273-1277

A low-cost through via interconnection for ISM WLP

(6) Yuan, Jingli a Jeung, Won Kyu a Lim, Chang Hyun a Park, Seung Wook a Kweon, Young Do a Yi, Sung a

a Samsung Electro Mechanics (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS IMAGE SENSOR; DEVICE WAFERS; ELECTRICAL CONNECTION; ELECTRICAL INTERCONNECTIONS; FABRICATION PROCESS; HIGH QUALITY; LARGE OPENINGS; LOW COSTS; PAD OXIDES; PASSIVATION LAYER; PHOTO IMAGES; PROCESS COSTS; RE-ROUTING; SENSOR DEVICE; SENSOR PACKAGING; SMALL SIZE; THROUGH-SILICON-VIA; UNIT PROCESS; VIA FILLING; VIA HOLE; VIA INTERCONNECTION; WAFER LEVEL PACKAGE; WAFER LEVEL PACKAGING;

COSTS; DIGITAL IMAGE STORAGE; ELECTRIC CONNECTORS; GLASS BONDING; IMAGE SENSORS; INTERCONNECTION NETWORKS; PASSIVATION; SILICON WAFERS; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 67649184767 PISSN: 09467076 EISSN: None Source Type: Journal
DOI: 10.1007/s00542-008-0766-1 Document Type: Conference Paper

Times cited : (8)

References (3)

1
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- Packaging technology for imager using through-hole interconnections in Si substrate
- 9.5, Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, HDP'04
- Hirafune S, Yamamoto S, Wada H, Okanishi K et al (2004) Packaging technology for imager using through-hole interconnection in Si substrate. In: Proceeding of HDP'04, IEEE, pp 303-306 (Pubitemid 40338976)
- (2004) Proceedings of the Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, HDP'04 , pp. 303-306
- Hirafune, S.¹ Yamamoto, S.² Wada, H.³ Okanishi, K.⁴ Tomita, M.⁵ Matsumaru, K.⁶ Suemasu, T.⁷

2
- 33845594162
- Novel low cost integration of through chip interconnection and application to CMOS image sensor
- DOI 10.1109/ECTC.2006.1645835, 1645835, Proceedings - IEEE 56th Electronic Components and Technology Conference
- Sekiguchi M, Numata H, Sato N, Shirakawa T et al (2006) Novel low cost integration of through chip interconnection and application to CMOS image sensor. In: Proceedings of the 56th electronic components and technology conference, 2006, 30 May-2 June 2006, pp 1367-1374 (Pubitemid 44929859)
- (2006) Proceedings - Electronic Components and Technology Conference , vol.2006 , pp. 1367-1374
- Sekiguchi, M.¹ Numata, H.² Sato, N.³ Shirakawa, T.⁴ Matsuo, M.⁵ Yoshikawa, H.⁶ Yanagida, M.⁷ Nakayoshi, H.⁸ Takahashi, K.⁹

3
- 33847309664
- Novel wafer level package technology studies for image sensor devices
- 7-9 Dec 2005
- Viswanadam G, Bieck F, Suthiwongsunthor N (2005) Novel wafer level package technology studies for image sensor devices. In: Proceedings of 7th electronic packaging technology conference, 2005, EPTC 2005, 7-9 Dec 2005, vol 1
- (2005) Proceedings of 7th Electronic Packaging Technology Conference, 2005, EPTC 2005 , vol.1
- Viswanadam, G.¹ Bieck, F.² Suthiwongsunthor, N.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.