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Volumn , Issue , 2005, Pages 5958-5961

A 2V 0.25μm CMOS 250MHz fully-differential seventh-order equiripple linear phase LF filter

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEMENTARY-DIFFERENTIAL; CROSS-COUPLED; EQUIRIPPLE; FULLY-DIFFERENTIAL; GAIN BOOST; GROUP DELAY RIPPLES; HIGH FREQUENCY OPERATION; LINEAR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER; LINEAR PHASE; LOW-DISTORTION; MAXIMUM POWER; MULTIPLE-LOOP FEEDBACK; POWER SUPPLY; REGULATED CASCODE; TOTAL HARMONIC DISTORTIONS;

EID: 67649133081     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465996     Document Type: Conference Paper
Times cited : (14)

References (10)
  • 2
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    • A CMOS fully-balanced continuous-time IFLF filter design for read/write channels
    • D. H. Chiang and R. Schaumann, "A CMOS fully-balanced continuous-time IFLF filter design for read/write channels", Proc. IEEE Int. Symp. Circuits and Systems, pp. 167-170, 1996.
    • (1996) Proc. IEEE Int. Symp. Circuits and Systems , pp. 167-170
    • Chiang, D.H.1    Schaumann, R.2
  • 4
    • 84963884905 scopus 로고
    • A 27MHz programmable bipolar 0.05° equiripple linear phase low pass filter. in IEEE ISSCC Dig
    • Feb
    • G. A. De Veirman and R. Yamasaki, "A 27MHz programmable bipolar 0.05° equiripple linear phase low pass filter." in IEEE ISSCC Dig. Tech. paper, pp. 64-65, Feb. 1992.
    • (1992) Tech. paper , pp. 64-65
    • De Veirman, G.A.1    Yamasaki, R.2
  • 6
    • 67649118607 scopus 로고    scopus 로고
    • N. Rao, V. Balan, and R. Contreras, A 3V 10-100MHz continuous-time seventh-order equiripple linear phase filter, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. papers, pp.44-46, Feb. 1999.
    • N. Rao, V. Balan, and R. Contreras, "A 3V 10-100MHz continuous-time seventh-order equiripple linear phase filter," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. papers, pp.44-46, Feb. 1999.
  • 7
    • 0031189288 scopus 로고    scopus 로고
    • A 50-MHz standard CMOS pulse equalizer for hard disk read channels
    • July
    • W. Dehaene, M. S. J. Steyaert, and W. Sansen, "A 50-MHz standard CMOS pulse equalizer for hard disk read channels", IEEE J. Solid-State Circuits, vol. 32, No.7, pp.977-988, July 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.7 , pp. 977-988
    • Dehaene, W.1    Steyaert, M.S.J.2    Sansen, W.3
  • 8
    • 0033280922 scopus 로고    scopus 로고
    • Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in sub micrometer CMOS
    • Dec
    • V. Gopinathan, M. Tarsia and D. Choi, "Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in sub micrometer CMOS", IEEE J. Solid-State Circuits, vol. 34, No.12, pp.1698-1707, Dec. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.12 , pp. 1698-1707
    • Gopinathan, V.1    Tarsia, M.2    Choi, D.3
  • 9
    • 0037321067 scopus 로고    scopus 로고
    • A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system
    • Feb
    • J. Silva-Martinez, J. Adut, J.M. Rocha-Perez, M. Robinson and S. Rokhsaz, "A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system", IEEE J. Solid-State Circuits, vol. 38, No.2, pp.216-225, Feb. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.2 , pp. 216-225
    • Silva-Martinez, J.1    Adut, J.2    Rocha-Perez, J.M.3    Robinson, M.4    Rokhsaz, S.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.