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Volumn , Issue , 2005, Pages 2987-2990

On the fault diagnosis in the presence of unknown fault models using pass/fail information

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT UNDER TEST; DIAGNOSTIC METHODS; FAULT DIAGNOSIS; FAULT MODEL; FAULTY CIRCUITS; FAULTY CONDITION; FEATURE SIZES; LOGIC VALUES; OPEN FAULTS; PRIMARY OUTPUTS; SINGLE STUCK-AT FAULTS; STUCK-AT FAULTS;

EID: 67649124674     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465255     Document Type: Conference Paper
Times cited : (5)

References (6)
  • 1
    • 0033336301 scopus 로고    scopus 로고
    • Fault diagnosis in scan-based BIST using both time and space information
    • J. G-Dastidar, D. Das, and N. A. Touba, "Fault diagnosis in scan-based BIST using both time and space information," in Proc. Int. Test Conf.,1999, pp. 95-102.
    • (1999) Proc. Int. Test Conf , pp. 95-102
    • G-Dastidar, J.1    Das, D.2    Touba, N.A.3
  • 2
    • 0002936338 scopus 로고
    • Carafe: An inductive fault analysis tool for CMOS VLSI circuits
    • A. Jee and F. J. Ferguson, "Carafe: An inductive fault analysis tool for CMOS VLSI circuits," in Proc. VLSI Test Symp., 1993, pp. 92-98.
    • (1993) Proc. VLSI Test Symp , pp. 92-98
    • Jee, A.1    Ferguson, F.J.2
  • 3
    • 0036446077 scopus 로고    scopus 로고
    • Multiplets, models, and the search for meaning improving per-test fault diagnosis
    • D. B. Lavo, I. Hartanto, and T. Larrabee, "Multiplets, models, and the search for meaning improving per-test fault diagnosis," in Proc. Int. Test Conf., 2002, pp. 250-259.
    • (2002) Proc. Int. Test Conf , pp. 250-259
    • Lavo, D.B.1    Hartanto, I.2    Larrabee, T.3
  • 4
    • 0036494690 scopus 로고    scopus 로고
    • On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits
    • Mar
    • H. Takahashi, K. O. Boateng, K. K. Saluja, and Y. Takamatsu, "On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits," IEEE Trans. on Computer-Aided Design, vol. 21(3), pp. 362-368, Mar. 2002.
    • (2002) IEEE Trans. on Computer-Aided Design , vol.21 , Issue.3 , pp. 362-368
    • Takahashi, H.1    Boateng, K.O.2    Saluja, K.K.3    Takamatsu, Y.4
  • 5
    • 0142216003 scopus 로고    scopus 로고
    • An efficient and effective methodology on the multiple fault diagnosis
    • Z. Wang, K. H. Tsai, M. M- Sadowska, and J. Rajski, "An efficient and effective methodology on the multiple fault diagnosis," in Proc. Int. Test Conf., 2003, pp. 329-338.
    • (2003) Proc. Int. Test Conf , pp. 329-338
    • Wang, Z.1    Tsai, K.H.2    Sadowska, M.M.3    Rajski, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.