Efficient frame-level pipelined array architecture for full-search block-matching motion estimation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2887-2890

  He, Wei Feng ^a   Bi, Yun Long ^a   Mao, Zhi Gang ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK-MATCHING MOTION ESTIMATION; DATA BROADCASTING; DESIGN EFFORT; DIGITAL TV; FEASIBLE SOLUTION; HARDWARE COST; HARDWARE OVERHEADS; PIPELINED ARRAY ARCHITECTURE; PROCESSOR UTILIZATION; SEARCH RANGE; SYSTOLIC ARRAY ARCHITECTURE; TEMPORAL REDUNDANCY; VIDEO COMPRESSION; VIDEO PICTURE FORMATS;

COMPUTER GRAPHICS; DIGITAL TELEVISION; ESTIMATION; IMAGE CODING; IMAGE COMPRESSION; TELEVISION BROADCASTING;

MOTION ESTIMATION;

EID: 67649094518     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465230     Document Type: Conference Paper

References (6)

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