On the implementation of 128-pt FFT/IFFT for high-performance WPAN

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5513-5516

  Huggett, Clare ^a   Maharatna, Koushik ^a   Paul, Kolin ^b  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

FFT ALGORITHM; FFT/IFFT; IEEE 802.15.3A; VIRTEX-II FPGA;

FAST FOURIER TRANSFORMS;

EID: 67349170945     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465885     Document Type: Conference Paper

References (6)

1. http://grouper.ieee.org/ groups/802/15/pub/2003/ May03/ 03142r1P802-15-TG3a-TI-CFP-Document.doc
2. I. S. Uzun and A. A. Bouridane, "FPGA Implementations of Fast Fourier Transforms for Real-Time Signals and Image Processing", Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), 2003.
3. http://www.xilinx.com/virtex2
4. R. J. Peterson and B. L. Hutchings, "An assessment of the suitability of FPGA-Based system design for use in DSP", 5th Intl Workshop on FPL and Application, Oxford, England August 1995.
5. A. M. Despain, "Very fast Fourier transform algorithms hardware for implementation", IEEE Trans. Comput., vol. C-28, no. 5, pp. 333 - 341, May 1979.
6. K. Maharatna, E. Grass and U. Jagdhold, "A 64-point Fourier transform chip for high-speed Wireless LAN application using OFDM", IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 484 - 493, March 2004.