Silicon nanowire NVM with high-k gate dielectric stack

Microelectronic Engineering

Volumn 86, Issue 7-9, 2009, Pages 1957-1960

  Zhu, Xiaoxiao ^a,b   Gu, D ^c,d   Li, Qiliang ^a,b   Ioannou, D E ^a   Baumgart, H ^c,d   Suehle, J S ^b   Richter, C A ^b  

^a Krasnow Institute for Advanced Study   (United States)

^b Novel Devices Group   (United States)

^c Old Dominion University   (United States)

^d THOMAS JEFFERSON NATIONAL ACCELERATOR FACILITY   (United States)

Author keywords

Flash memory; NVM; Silicon nanowire; SiNW

Indexed keywords

BLOCKING LAYERS; FAST OPERATION; FLASH MEMORY CELL; HIGH-K DIELECTRIC; HIGH-K GATE DIELECTRICS; MEMORY WINDOW; NVM; PLANAR CELLS; SELF-ALIGNING; SILICON NANOWIRE; SILICON NANOWIRES; SINW; TUNNELING OXIDES;

ALUMINUM; CELL MEMBRANES; CHARGE TRAPPING; ELECTRIC FIELDS; ELECTRIC WIRE; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; NANOWIRES; SILICON COMPOUNDS; SILICON OXIDES;

FLASH MEMORY;

EID: 67349120581     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.03.095     Document Type: Article

References (8)

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8. We identify certain commercial equipments, instruments or materials in this article to specify adequately the experimental procedure. In no case does such identification imply recommendation or endorsement by the National Institute of Standards and Technology, nor does it imply that the materials or equipment identified are necessarily the best available for the purpose.