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Volumn , Issue , 2008, Pages 1739-1743

A flexible and overlapped qc-ldpc decoder

Author keywords

[No Author keywords available]

Indexed keywords

CODE CONSTRUCTION; COMMUNICATION COMPLEXITY; DECODER DESIGNS; HIGH-THROUGHPUT; LDPC DECODER; LOW DENSITY PARITY CHECK; LOW-COMPLEXITY; MULTIPLE CODES; PARALLEL PROCESSING; QUASICYCLIC CODES; SEQUENTIAL PROCESSING; SERIAL PROCESSING; STRUCTURED CODES; SUB-MATRICES;

EID: 67249149655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICOSP.2008.4697474     Document Type: Conference Paper
Times cited : (2)

References (12)
  • 1
    • 0035248618 scopus 로고    scopus 로고
    • On the Design of Low-Density Parity-Check Codes within 0.0045dB of the Shannon Limit
    • February
    • S. Chung, G. Forney, J. Richardson, and R. Urbanke, "On the Design of Low-Density Parity-Check Codes within 0.0045dB of the Shannon Limit," IEEE Communication Let- ters, vol. 5, pp. 58-60, February 2001.
    • (2001) IEEE Communication Let- ters , vol.5 , pp. 58-60
    • Chung, S.1    Forney, G.2    Richardson, J.3    Urbanke, R.4
  • 2
    • 67249162297 scopus 로고    scopus 로고
    • M. Eroz, F. Sun, and L. Lee
    • M. Eroz, F. Sun, and L. Lee
  • 4
    • 33645807178 scopus 로고    scopus 로고
    • Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder
    • April
    • L. Yang, H. Liu, and C. Shi, "Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder," IEEE Transac- tions on Circuits and Systems-I, vol. 53, pp. 892-904, April 2006.
    • (2006) IEEE Transac- tions on Circuits and Systems-I , vol.53 , pp. 892-904
    • Yang, L.1    Liu, H.2    Shi, C.3
  • 6
    • 34347358635 scopus 로고    scopus 로고
    • G. Malema and M. Liebelt, Quasi-Cyclic LDPC Codes of Column-Weight Two Using a Search Algorithm, EURASIP Journal on Advances in Signal Processing, 2007, pp. Ar- ticle ID 45768, 8 pages, 2007.
    • G. Malema and M. Liebelt, "Quasi-Cyclic LDPC Codes of Column-Weight Two Using a Search Algorithm," EURASIP Journal on Advances in Signal Processing, vol. 2007, pp. Ar- ticle ID 45768, 8 pages, 2007.
  • 8
    • 33750918495 scopus 로고    scopus 로고
    • Scheduling Algorithm for Partially Parallel Architecture of LDPC Decoder by Matrix Permu- tation
    • May
    • I. Park and S. Kang, "Scheduling Algorithm for Partially Parallel Architecture of LDPC Decoder by Matrix Permu- tation," IEEE International Symposium on Circuits and Sys- tems, pp. 5778-5781, May 2005.
    • (2005) IEEE International Symposium on Circuits and Sys- tems , pp. 5778-5781
    • Park, I.1    Kang, S.2
  • 9
    • 3042549356 scopus 로고    scopus 로고
    • Overlapped Message Passing for Quasi-Cyclic Low-Density Parity-Check Codes
    • June
    • Y. Chen and K. Parhi, "Overlapped Message Passing for Quasi-Cyclic Low-Density Parity-Check Codes," IEEE Transactions on Circuits and Systems, vol. 51, pp. 1106-1113, June 2004.
    • (2004) IEEE Transactions on Circuits and Systems , vol.51 , pp. 1106-1113
    • Chen, Y.1    Parhi, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.