Enhanced layout optimization of sub-45nm standard, memory cells and its effects

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7275, Issue , 2009, Pages

  Paek, Seung Weon ^a   Jang, Dae Hyun ^a   Park, Joo Hyun ^a   Ha, Naya ^a   Kim, Byung Moo ^a   Won, Hyo Sig ^a   Choi, Kyu Myung ^a   Lin, Kuang Kuo ^b   Klaver, Simon ^c   Malik, Shobhit ^c   Oostindie, Michiel ^c   Driessen, Frank ^c  

^a Takumi Technology Corporation   (United States)

^b Chartered Semiconductor Manufacturing Inc

^c SAMSUNG Electronics   (South Korea)

Author keywords

CAA; DfM kit(s); DfM validation; Leaf cell(s); Litho; Memory compilers; Primitive cell(s); Recommended rule; Trade off

Indexed keywords

CAA; DFM KIT(S); DFM VALIDATION; LEAF-CELL(S); LITHO; MEMORY COMPILERS; PRIMITIVE CELL(S); RECOMMENDED RULE; TRADE-OFF;

COMMERCE; ELECTRIC BATTERIES; MACHINE DESIGN; MODEL CHECKING; OPTIMIZATION; PROGRAM COMPILERS; STANDARDS;

CELLS;

EID: 66749109534     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.815413     Document Type: Conference Paper

References (9)

1. Chiang, C.; Kawa, J. "Three DfM Challenges: Random Defects, Thickness Variation, and Printability Variation " Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on, 4-7 Dec. 2006 Page(s):1099
2. Robert Aitken, " DfM Metrics for Standard Cells " proceedings of the 7th International Symposium on quality Electronics Design (ISQED'2006).
3. Maynard, D.N.; Runyon, S.L.; Reuter, B.B. "Yield Enhancement Using Recommended Ground Rules " Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop, 4-6 May 2004 Page(s):98 - 104
4. Schellenberg, F.M." Design for Manufacturing in the Semiconductor Industry : The Litho / Design Workshops, VLSI Design, 1999. Proceedings. Twelfth International Conference On 7-10 Jan. 1999 Page(s):111 - 119.
5. K. Peter, R. März, and S. Gröndahl, "Litho-Friendly Design (LFD) methodologies applied to library cells," Proc SPIE (2006), vol. 6349, no. 14.
6. Riviere-Cazaux, L.; Lucas, K.; Fitch, J. , "Integration Of Design For Manufacturability (DfM) Practices In Design Flows." Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 21-23 March 2005 Page(s):102 - 106.
7. Shi-Hao Chen; Ke-Cheng Chu; Jiing-Yuan Lin; Cheng-Hong Tsai, " DfM/DFY practices during physical designs for timing, signal integrity, and power" Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific, 23-26 Jan. 2007 Page(s):232 -
8. Mark E. Mason " DfM EDA Technology : A Lithographic Perspective " Symposium on VLSI Technology Digest of Technical Papers, June(2005), page : 90-91.
9. Carlo Guardiani, Massimo Bertoletti,Nicola Dragone, Macro Malcotti, and Patrick McNamara, "An Effective DfM Strategy Accurate Process and IP Pre-Characterization" DAC 2005, June 13-17, (2005).