New designs and materials tackle 1 Gb memory challenge

Semiconductor International

Volumn 23, Issue 13, 2000, Pages 83-84,-86,-88,-90

  Baliga, John ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHEMICAL VAPOR DEPOSITION; DIELECTRIC MATERIALS; ETCHING; LITHOGRAPHY; PERFORMANCE; SEMICONDUCTOR DEVICE STRUCTURES; SURFACE STRUCTURE;

DESIGN INNOVATION; MEMORY DENSITY; PATTERNING; SCALING;

DATA STORAGE EQUIPMENT;

EID: 6644228470     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. JEDEC Standard no. 100-B, Terms, Definitions and Letter Symbols for Microcomputers, Microprocessors and Memory Integrated Circuits.
2. 1999 International Technology Roadmap for Semiconductors
3. C. Radens et al, "An Orthogonal 6F2 Trench-Sidewall Vertical Device for 4 Gb/16 Gb DRAM," IEDM 2000.
4. T. Kajiyama et al, "Diagonal Layout & Surface Strap Trench (DST cell)," IEDM 2000.
5. G. Zhang, "Improving IC Yield with Protective Ceramics," Semiconductor International, June 2000.
6. J. Baliga, "New Materials Enhance Memory Performance," Semiconductor International, Nov 1999.
7. 3 Thin Films by Atomic Layer Deposition," Electrochemical and Solid State Letters, Vol. 2, No. 10, 1999.
8. N. Inoue et al, "Low Thermal-Budget Fabrication of Sputtered-PZT Capacitor on Multilevel Interconnects for Embedded FeRAM," IEDM 2000.
9. 2/Ir Capacitor for a Highly Reliable Mega-Scale FRAM," IEDM 2000.