SCOPUS 정보 검색 플랫폼

Volumn 94, Issue 15, 2009, Pages

The Fermi-level efficiency method and its applications on high interface trap density oxide-semiconductor interfaces

(9) Lin, H C a Brammertz, Guy a Martens, Koen a De Valicourt, Guilhem b Negre, Laurent b Wang, Wei E c Tsai, Wilman c Meuris, Marc a Heyns, Marc a

a IMEC (Belgium)

b INSA (France)

c INTEL CORPORATION (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONDUCTANCE METHODS; ENERGY RELATIONS; GATE BIAS; INTERFACE CHARACTERIZATIONS; INTERFACE QUALITIES; INTERFACE TRAP DENSITIES; METAL-OXIDE SEMICONDUCTORS; SEMICONDUCTOR INTERFACES; SUBSTRATE MATERIALS; TRAP DENSITIES;

CHARGE TRAPPING; ELECTRIC CONDUCTIVITY; FERMIONS; MOSFET DEVICES; PASSIVATION; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES;

SEMICONDUCTOR MATERIALS;

EID: 65249175032 PISSN: 00036951 EISSN: None Source Type: Journal
DOI: 10.1063/1.3113523 Document Type: Article

Times cited : (57)

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