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Volumn 33, Issue 3, 2009, Pages 221-231

An 8-bit systolic AES architecture for moderate data rate applications

Author keywords

Advanced Encryption Standard (AES); Cryptography; Low power; Security

Indexed keywords

ADVANCED ENCRYPTION STANDARD (AES); ADVANCED ENCRYPTION STANDARD ALGORITHMS; AES ALGORITHMS; ARCHITECTURAL TRANSFORMATIONS; BIT-OPERATIONS; COLUMN DESIGNS; COMPARISON RESULTS; COMPLEX MATRICES; COMPLEX PARTS; DATA PATHS; DATA RATE APPLICATIONS; DATA RATES; ENCRYPTION/DECRYPTION; KEY EXPANSIONS; LOGIC RESOURCES; LOW POWER; NON-LINEAR; POWER DISSIPATIONS; SECURITY; SECURITY SOLUTIONS; SERIAL ARCHITECTURES; SYSTOLIC ARCHITECTURES;

EID: 64849108004     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2009.02.013     Document Type: Article
Times cited : (11)

References (15)
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    • FIPS 197, Federal Information Processing Standards Publication (FIPS) 197, Specification for the Advanced Encryption Standard (AES), NIST's AES, November 26, 2001. Available from: .
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  • 5
    • 0019596071 scopus 로고
    • Trace scheduling: a technique for global microcode compaction
    • Fisher J.A. Trace scheduling: a technique for global microcode compaction. IEEE Transactions on Computers c-30 7 (1981) 478-490
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    • Fisher, J.A.1
  • 6
    • 34548306694 scopus 로고    scopus 로고
    • Monjur Alam Sonai, Ray Debdeep Mukhopadhayay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta, An area optimized reconfigurable encryptor for AES-Rijndael, in: Proceedings of Design, Automation and Test in Europe (DATE07), Nice, France, pp. 1116-1121.
    • Monjur Alam Sonai, Ray Debdeep Mukhopadhayay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta, An area optimized reconfigurable encryptor for AES-Rijndael, in: Proceedings of Design, Automation and Test in Europe (DATE07), Nice, France, pp. 1116-1121.
  • 12
    • 33746081664 scopus 로고    scopus 로고
    • Very Small FPGA Application-Specific Instruction Processor for AES
    • Regular Papers, July
    • Tim Good, Mohammed Benaissa, Very Small FPGA Application-Specific Instruction Processor for AES, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 53(7), July 2006, pp. 1477-1486.
    • (2006) IEEE Transactions on Circuits and Systems-I , vol.53 , Issue.7 , pp. 1477-1486
    • Good, T.1    Benaissa, M.2
  • 13
    • 21644436204 scopus 로고    scopus 로고
    • Mapping of high bit algorithm to low bit for optimized hardware implementation
    • Tunis, Tunisia, December 6-8
    • Sheikh M. Farhan, Shoab A. Khan, Habibullah Jamal, Mapping of high bit algorithm to low bit for optimized hardware implementation, in: Proceedings of 16th International Conference on Microelectronics, ICM 2004, Tunis, Tunisia, December 6-8, 2004, pp. 148-151.
    • (2004) Proceedings of 16th International Conference on Microelectronics, ICM , pp. 148-151
    • Farhan, S.M.1    Khan, S.A.2    Jamal, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.