Compound semiconductor as cmos channel material: Déjà vu or new paradigm?

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2008, Pages 33-36

  Datta, Suman ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 64849097956     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2008.4800724     Document Type: Conference Paper

References (6)

1. S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, D. Wallis, P. Wilding and R. Chau, "85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications," IEDM Technical Digest, pp. 763-766, Washington, DC, December 5-7, 2005
2. R. Chau, B. Doyle, S. Datta, K. Kavalieros and K. Zhang, "Integrated nanoelectronics for the future," Nature Materials, vol. 6, pp. 810-812, 2007
3. S. Datta, G. Dewey, J. M. Fastenau, M. K. Hudait, D. Loubychev, W. K. Liu, M. Radosavljevic, W. Rachmady and R. Chau, "Ultrahigh-Speed 0.5 V Supply Voltage InO.7GaO.3As Quantum-Well Transistors on Silicon Substrate," IEEE Electron Device Letters, Vol. 28, No. 8, pp. 685, 2007.
4. S. Datta, "III-V field-effect transistors for low power digital logic applications," Journal of Microelectronic Engineering, Vol. 84, No. 9-10, pp. 2133-2137, 2007
5. M. K. Hudait, S. Datta, G. Dewey, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, M. Radosavljevic and R. Chau, "Heterogeneous Integration of Enhancement Mode InO.7GaO.3As Quantum Well Transistor on Silicon Substrate using Thin (<2 um) Composite Buffer Architecture for High-Speed and Low-voltage (0.5V) Logic Applications," International Electron Devices Meeting (IEDM) Technical Digest, pp. 625-628, Washington, DC, December 10-12, 2007
6. S. Mookerjea and S. Datta "Comparative Study of Si, Ge and InAs based Steep Sub Threshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications," accepted for presentation at the Device Research Conference '08, University of California, Santa Barbara.