메뉴 건너뛰기




Volumn 56, Issue 2, 2009, Pages 366-374

A comprehensive methodology for complex field programmable gate array single event effects test and evaluation

Author keywords

Evaluation; FPGA; Scrubbing; Triple Mode Redundancy (TMR)

Indexed keywords

EVALUATION; FPGA; OPTIMAL DEVICES; SCRUBBING; SINGLE EVENT EFFECTS; SPACE MISSIONS; TEST AND EVALUATIONS; TRIPLE MODE REDUNDANCY (TMR);

EID: 64749091920     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2009.2013857     Document Type: Article
Times cited : (11)

References (16)
  • 1
    • 64749087977 scopus 로고    scopus 로고
    • Online, Available:, Oct. 2007
    • Actel Datasheet, RTAX-S/SL RadTolerant FPGAs [Online]. Available: http://www.actel.com/documents/RTAXS-DS.pdf V5.2, Oct. 2007
    • SL RadTolerant FPGAs
  • 2
    • 64749093836 scopus 로고    scopus 로고
    • Xilinx Virtex-4 Data Sheet: And Switching Characteristics [Online]. Available: http://www.xilinx.com/support/documentation/data-sheets/ds302.pdf
    • Xilinx Virtex-4 Data Sheet: And Switching Characteristics [Online]. Available: http://www.xilinx.com/support/documentation/data-sheets/ds302.pdf
  • 3
    • 64749103743 scopus 로고    scopus 로고
    • Online, Available
    • Aeroflex Datasheet [Online]. Available: http://ams.aeroflex.com/ ProductFiles/DataSheets/FPGA/RadHardEclipseFPGA.pdf
    • Aeroflex Datasheet
  • 4
    • 37249090735 scopus 로고    scopus 로고
    • New methodologies for SET characterization and mitigation in flash-based FPGAs
    • Dec
    • S. Rezgui, J. Wang, E. Tung, B. Cronquist, and J. McCollum, "New methodologies for SET characterization and mitigation in flash-based FPGAs," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2512-2524, Dec.2007.
    • (2007) IEEE Trans. Nucl. Sci , vol.54 , Issue.6 , pp. 2512-2524
    • Rezgui, S.1    Wang, J.2    Tung, E.3    Cronquist, B.4    McCollum, J.5
  • 5
    • 33846387083 scopus 로고    scopus 로고
    • An analysis of single event upset dependencies on high frequency and architectural implementations within Actel RTAX-S family field programmable gate arrays
    • Dec
    • M. Berg, "An analysis of single event upset dependencies on high frequency and architectural implementations within Actel RTAX-S family field programmable gate arrays," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3569 -3574, Dec. 2006.
    • (2006) IEEE Trans. Nucl. Sci , vol.53 , Issue.6 , pp. 3569-3574
    • Berg, M.1
  • 9
    • 44449109736 scopus 로고    scopus 로고
    • Development of a low cost and high speed single event effects tester based on reconfigurable Field Programmable Gate Arrays (FPGA)
    • presented at the, Long Beach, CA, Apr
    • J. W. Howard et al., "Development of a low cost and high speed single event effects tester based on reconfigurable Field Programmable Gate Arrays (FPGA)," presented at the SEE Symp., Long Beach, CA, Apr. 2006.
    • (2006) SEE Symp
    • Howard, J.W.1
  • 10
    • 0024172398 scopus 로고
    • Comparison of error rates in combinatorial logic and sequential logic
    • Dec
    • S. Buchner, M. Baze, D. Brown, D. McMarrow, and J. Melinger, "Comparison of error rates in combinatorial logic and sequential logic," IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1517-1522, Dec. 1988.
    • (1988) IEEE Trans. Nucl. Sci , vol.35 , Issue.6 , pp. 1517-1522
    • Buchner, S.1    Baze, M.2    Brown, D.3    McMarrow, D.4    Melinger, J.5
  • 11
    • 70449587176 scopus 로고    scopus 로고
    • Single Event Effects (SEE) response of embedded power PCs in a Xilinx Virtex-4 FPGA for a space application
    • presented at the, Deauville, France, Sep
    • C. Poivey,M. Berg, and K. A. LaBel et al., "Single Event Effects (SEE) response of embedded power PCs in a Xilinx Virtex-4 FPGA for a space application," presented at the RADECS Conf., Deauville, France, Sep. 2007.
    • (2007) RADECS Conf
    • Poivey, C.1    Berg, M.2    LaBel, K.A.3
  • 16
    • 84954092841 scopus 로고    scopus 로고
    • SEE mitigation strategies for digital circuit design applicable to ASIC and FPGAs
    • presented at the, Honolulu, HI, Jul. 23, Short Course
    • F. Kastensmidt, "SEE mitigation strategies for digital circuit design applicable to ASIC and FPGAs," presented at the Nuclear and Space Radiation Effects Conf., Honolulu, HI, Jul. 23, 2007, Part II, Short Course.
    • (2007) Nuclear and Space Radiation Effects Conf , Issue.PART II
    • Kastensmidt, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.