TDDB in the presence of interface states: Implications for the PMOS reliability margin

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Nigam, T ^a   Peumans, P ^b  

^a Stanford University ^*  (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; VOLTAGE SCALING;

INTERFACE DEFECTS; LOW VOLTAGES; PRODUCT LIFETIME; RELIABILITY MARGIN; ULTRA THIN GATE OXIDE;

INTERFACE STATES;

EID: 64549163613     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796814     Document Type: Conference Paper

References (8)

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