Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Salvatore, Giovanni A ^a   Bouvet, Didier ^a   Ionescu, Adrian Mihai ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

FERROELECTRIC GATES; FERROELECTRIC LAYERS; GATE STACKS; MOS FETS; MOS TRANSISTORS; NEGATIVE CAPACITANCES; ROOM TEMPERATURES; SUB-THRESHOLD SWINGS; VOLTAGE AMPLIFICATIONS;

AMPLIFICATION; CAPACITANCE; ELECTRON DEVICES; FERROELECTRICITY; FIELD EFFECT TRANSISTORS; MESFET DEVICES; SILICON COMPOUNDS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

LOGIC GATES;

EID: 64549084475     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796642     Document Type: Conference Paper

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