-
3
-
-
84957376851
-
-
BRAYTON, R. K., HACHTEL, G. D., SANGIOVANNI- VINCENTELLI, A., SOMENZI, F., AZIZ, A., CHENG, S.-T., EDWARDS, S., KHATRI, S., KUKIMOTO, Y., PARDO, A., QADEER, S., RANJAN, R. K., SARWARY, S., SHIPLE, T. R., SWAMY, G., AND VILLA, T. Vis: A system for verification and synthesis. In Eigth Conference on Computer Aided Verification (CAV'96), T. Henzinger and R. Alur, Eds. Springer-Verlag, Rutgers University, 1996, pp. 428-432. LNCS 1102.
-
BRAYTON, R. K., HACHTEL, G. D., SANGIOVANNI- VINCENTELLI, A., SOMENZI, F., AZIZ, A., CHENG, S.-T., EDWARDS, S., KHATRI, S., KUKIMOTO, Y., PARDO, A., QADEER, S., RANJAN, R. K., SARWARY, S., SHIPLE, T. R., SWAMY, G., AND VILLA, T. Vis: A system for verification and synthesis. In Eigth Conference on Computer Aided Verification (CAV'96), T. Henzinger and R. Alur, Eds. Springer-Verlag, Rutgers University, 1996, pp. 428-432. LNCS 1102.
-
-
-
-
4
-
-
0022769976
-
Graph-based algorithms for Boolean function manipulation
-
August
-
BRYANT, R. E. Graph-based algorithms for Boolean function manipulation. IEEE Transaction on Computers C-35, 8 (August 1986), 677-691.
-
(1986)
IEEE Transaction on Computers
, vol.C-35
, Issue.8
, pp. 677-691
-
-
BRYANT, R.E.1
-
6
-
-
79959411439
-
FastForward for efficient pipeline parallelism: A cache-optimized concurrent lock-free queue
-
GIACOMONI, J., MOSELEY, T., AND VACHHARAJANI, M. FastForward for efficient pipeline parallelism: A cache-optimized concurrent lock-free queue. In PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (2008), pp. 43-52.
-
(2008)
PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
, pp. 43-52
-
-
GIACOMONI, J.1
MOSELEY, T.2
VACHHARAJANI, M.3
-
7
-
-
0032305982
-
-
III, J. H., AND BRGLEZ, F. Design of experiments in BDD variable ordering:lessons learned. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (1998), pp. 646-652.
-
III, J. H., AND BRGLEZ, F. Design of experiments in BDD variable ordering:lessons learned. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (1998), pp. 646-652.
-
-
-
-
8
-
-
63549103012
-
Finding parallelism for future EPIC machines
-
March
-
IYER, M., ASHOK, C., STONE, J., VACHHARAJANI, N., CONNORS, D. A., AND VACHHARAJANI, M. Finding parallelism for future EPIC machines. In Proceedings of the 4th Workshop on Explicitly Parallel Instruction Computing Techniques (EPIC) (March 2005).
-
(2005)
Proceedings of the 4th Workshop on Explicitly Parallel Instruction Computing Techniques (EPIC)
-
-
IYER, M.1
ASHOK, C.2
STONE, J.3
VACHHARAJANI, N.4
CONNORS, D.A.5
VACHHARAJANI, M.6
-
9
-
-
33749929259
-
Variable ordering for binary decision diagrams
-
JEONG, S.-W., PLESSIER, B., HACHTEL, G., AND SOMENZI, F. Variable ordering for binary decision diagrams. In Proceedings of the 3rd European Design Automation Conference (1992), pp. 447-451.
-
(1992)
Proceedings of the 3rd European Design Automation Conference
, pp. 447-451
-
-
JEONG, S.-W.1
PLESSIER, B.2
HACHTEL, G.3
SOMENZI, F.4
-
12
-
-
33749375700
-
Automatic thread extraction with decoupled software pipelining
-
OTTONI, G., RANGAN, R., STOLER, A., AND AUGUST, D. I. Automatic thread extraction with decoupled software pipelining. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2005), pp. 105-118.
-
(2005)
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO
, pp. 105-118
-
-
OTTONI, G.1
RANGAN, R.2
STOLER, A.3
AUGUST, D.I.4
-
13
-
-
63549094807
-
Performance limits of trace caches
-
Tech. Rep. CSE-TR-373-98, University of Maryland, Department of Electrical Engineering and Computer Science, CSE, September
-
POSTIFF, M., TYSON, G., AND MUDGE, T. Performance limits of trace caches. Tech. Rep. CSE-TR-373-98, University of Maryland, Department of Electrical Engineering and Computer Science, CSE, September 1998.
-
(1998)
-
-
POSTIFF, M.1
TYSON, G.2
MUDGE, T.3
-
15
-
-
10444243253
-
-
RANGAN, R., VACHHARAJANI, N., VACHHARAJANI, M., AND AUGUST, D. I. Decoupled software pipelining with the synchronization array. In 13th International Conference on Parallel Architectures and Compilation Techniques (PACT) (September 2004), pp. 177-188.
-
RANGAN, R., VACHHARAJANI, N., VACHHARAJANI, M., AND AUGUST, D. I. Decoupled software pipelining with the synchronization array. In 13th International Conference on Parallel Architectures and Compilation Techniques (PACT) (September 2004), pp. 177-188.
-
-
-
-
17
-
-
84869274216
-
-
SOMENZI, F. CUDD: Colorado University Decision Diagram package, release 2.30. Tech. rep, University of Colorado at Boulder, 1998
-
SOMENZI, F. CUDD: Colorado University Decision Diagram package, release 2.30. Tech. rep., University of Colorado at Boulder, http://vlsi.colorado.edu/~fabio/CUDD/, 1998.
-
-
-
-
18
-
-
63549093892
-
-
VACHHARAJANI, N., IYER, M., ASHOK, C., VACHHARAJANI, M., AUGUST, D. I., AND CONNORS, D. A. Chip multi-processor scalability for single-threaded applications. In Proceedings of the 2005 Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) (November 2005).
-
VACHHARAJANI, N., IYER, M., ASHOK, C., VACHHARAJANI, M., AUGUST, D. I., AND CONNORS, D. A. Chip multi-processor scalability for single-threaded applications. In Proceedings of the 2005 Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP) (November 2005).
-
-
-
-
19
-
-
0003886621
-
Limits of instruction-level parallelism
-
Tech. Rep. 93/6, DEC WRL, November
-
WALL, D. W. Limits of instruction-level parallelism. Tech. Rep. 93/6, DEC WRL, November 1993.
-
(1993)
-
-
WALL, D.W.1
-
21
-
-
0038262825
-
Precise dynamic slicing algorithms
-
May
-
ZHANG, X., GUPTA, R., AND ZHANG, Y. Precise dynamic slicing algorithms. In Proceedings of the 25th International Conference on Software Engineering (ICSE) (May 2003), pp. 319-329.
-
(2003)
Proceedings of the 25th International Conference on Software Engineering (ICSE
, pp. 319-329
-
-
ZHANG, X.1
GUPTA, R.2
ZHANG, Y.3
-
22
-
-
4544331311
-
-
ZHANG, X., GUPTA, R., AND ZHANG, Y. Efficient forward computation of dynamic slices using reduced ordered binary decision diagrams. In Procedings of the 26th International conference on Software Engineering (ICSE) (2004).
-
ZHANG, X., GUPTA, R., AND ZHANG, Y. Efficient forward computation of dynamic slices using reduced ordered binary decision diagrams. In Procedings of the 26th International conference on Software Engineering (ICSE) (2004).
-
-
-
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