Power reduction via an MTCMOS implementation of MOS current mode logic

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 193-197

  Anis, Mohab H ^a   Elmasry, Mohamed I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRASHWORTHINESS; EMITTER COUPLED LOGIC CIRCUITS; FREQUENCY RESPONSE; THRESHOLD VOLTAGE;

CIRCUIT PARAMETER; COMMON MODE REJECTION RATIO; CURRENT MATCHING; HIGH SPEED IMPLEMENTATION; MOS CURRENT-MODE LOGIC; MULTI-THRESHOLD CMOS; POWER REDUCTIONS; THRESHOLD VOLTAGE FLUCTUATIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 84949458622     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158055     Document Type: Conference Paper

References (8)

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2. M, Mizuno et. al., ''A GHz. MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic," in IEEE J. Solid-State Circuits. VOL.31, pp. 784-791. June 1996.
3. J. Musicer and J. Rabaey. "MOS Current Mode Logic for Low Power, Low Noise CORDIC Computations in Mixed-Signal Environments:' in ISLPED'00 pp, 102-107, July 2000.
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5. L. Wei et al,, "Design and optimization of dual-threshold circuit for low-voltage low-power applica tions." IEEE Trans. on VLSI Systems. pp. 16-24. 1999.
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8. P.Gray and R.Meyer. Analysis and Design of Analog Integrated Circuits. New York: Wiley. 1993.